vishay siliconix SUM70N04-07l document number: 72345 s-80274-rev. b, 11-feb-08 www.vishay.com 1 n-channel 40-v (d-s) 175 c mosfet features ? trenchfet ? power mosfet ? 175 c junction temperature ? low threshold applications ? motor control product summary v (br)dss (v) r ds(on) ( )i d (a) 40 0.0074 at v gs = 10 v 70 a 0.011 at v gs = 4.5 v 67 to-263 s d g top view ordering information: SUM70N04-07l-e3 (lead (pb)-free) d g s n-channel mosfe t notes: a. package limited. b. duty cycle 1 %. c. see soa curve for voltage derating. d. when mounted on 1" square pcb (fr-4 material). * pb containing terminations are not rohs compliant, exemptions may apply. absolute maximum ratings t c = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds 40 v gate-source voltage v gs 20 continuous drain current (t j = 175 c) t c = 25 c i d 70 a a t c = 125 c 47 pulsed drain current i dm 120 avalanche current i ar 40 repetitive avalanche energy b l = 0.1 mh e ar 80 mj maximum power dissipation b t c = 25 c p d 100 c w t a = 25 c d 3.75 operating junction and storage temperature range t j , t stg - 55 to 175 c thermal resistance ratings parameter symbol limit unit junction-to-ambient pcb mount d r thja 40 c/w junction-to-case r thjc 1.4 a v aila b le rohs* compliant
www.vishay.com 2 document number: 72345 s-80274-rev. b, 11-feb-08 vishay siliconix SUM70N04-07l notes: a. pulse test; pulse width 300 s, duty cycle 2 %. b. guaranteed by design, not subject to production testing. c. independent of operating temperature. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v (br)dss v ds = 0 v, i d = 250 a 40 v gate-threshold voltage v gs(th) v ds = v gs , i d = 250 a 13 gate-body leakage i gss v ds = 0 v, v gs = 20 v 100 na zero gate voltage drain current i dss v ds = 32 v, v gs = 0 v 1 a v ds = 32 v, v gs = 0 v, t j = 125 c 50 v ds = 32 v, v gs = 0 v, t j = 175 c 250 on-state drain current a i d(on) v ds 5 v, v gs = 10 v 100 a drain-source on-state resistance a r ds(on) v gs = 10 v, i d = 30 a 0.006 0.0074 v gs = 4.5 v, i d = 10 a 0.0085 0.011 v gs = 10 v, i d = 30 a, t j = 125 c 0.012 v gs = 10 v, i d = 30 a, t j = 175 c 0.015 forward transconductance a g fs v ds = 15 v, i d = 30 a 20 s dynamic b input capacitance c iss v gs = 0 v, v ds = 25 v, f = 1 mhz 2800 pf output capacitance c oss 320 reverse transfer capacitance c rss 190 total gate charge c q g v ds = 20 v, v gs = 10 v, i d = 50 a 50 75 nc gate-source charge c q gs 10 gate-drain charge c q gd 10 gate resistance r g 2.0 tu r n - o n d e l ay t i m e c t d(on) v dd = 20 v, r l = 0.4 i d ? 50 a, v gen = 10 v, r g = 2.5 11 20 ns rise time c t r 20 30 turn-off delay time c t d(off) 40 60 fall time c t f 15 25 source-drain diode ratings and characteristics t c = 25 c b continuous current i s 66 a pulsed current i sm 100 forward voltage a v sd i f = 50 a, v gs = 0 v 1.0 1.5 v reverse recovery time t rr i f = 50 a, di/dt = 100 a/s 30 50 ns peak reverse recovery current i rm(rec) 1.6 2.4 a reverse recovery charge q rr 0.024 0.06 c
document number: 72345 s-80274-rev. b, 11-feb-08 www.vishay.com 3 vishay siliconix SUM70N04-07l typical characteristics 25 c, unless otherwise noted output characteristics transconductance capacitance 0 20 40 60 80 100 0123456 v ds - drain-to-source voltage (v) 3 v v gs = 10 thru 5 v 4 v - drain current (a) i d 0 30 60 90 120 150 0 102030405060 - transconductance (s) g fs t c = - 55 c 25 c 125 c i d - drain current (a) 0 800 1600 2400 3200 4000 0 8 16 24 32 40 v ds - drain-to-source voltage (v) c - capacitance (pf) c iss c oss c rss transfer characteristics on-resistance vs. drain current gate charge 0 20 40 60 80 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v gs - gate-to-source voltage (v) - drain current (a) i d 25 c - 55 c t c = 125 c 0.000 0.004 0.008 0.012 0.016 0 20406080100 i d - drain current (a) v gs = 10 v v gs = 4.5 v - on-resistance ( ) r ds(on) 0 2 4 6 8 10 0 1020304050 - gate-to-source voltage (v) q g - total gate charge (nc) v gs v ds = 20 v i d = 50 a
www.vishay.com 4 document number: 72345 s-80274-rev. b, 11-feb-08 vishay siliconix SUM70N04-07l typical characteristics 25 c, unless otherwise noted on-resistance vs. junction temperature 0.5 0.8 1.1 1.4 1.7 2.0 - 50 - 25 0 25 50 75 100 125 150 175 t j - junction temperature ( c) v gs = 10 v i d = 20 a (normalized) - on-resistance r ds(on) source-drain diode forward voltage v sd - source-to-drain voltage (v) - source current (a) i s 100 10 1 0.3 0.6 0.9 1.2 t j = 25 c t j = 150 c 0 drain source breakdown vs. junction temperature 42 44 46 48 50 52 54 - 50 - 25 0 25 50 75 100 125 150 175 t j - junction temperature (c) (v) v (br)dss i d = 10 ma
document number: 72345 s-80274-rev. b, 11-feb-08 www.vishay.com 5 vishay siliconix SUM70N04-07l thermal ratings vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?72345. maximum avalanche and drain current vs. case temperature 0 20 40 60 80 100 0 25 50 75 100 125 150 175 t c - case temperature (c) - drain current (a) i d limited by package safe operating area, junction-to-case 1000 10 0.1 1 10 100 0.1 100 t c = 25 c single pulse - drain current (a) i d 1 ms 10 ms dc, 100 ms 10 s 100 s 1 limited by r ds(on) * v ds - drain-to-source voltage (v) * v gs minimum v gs at which r ds(on) is specified normalized thermal transient impedance, junction-to-case square wave pulse duration (s) 2 1 0.1 0.01 10 -4 10 -3 10 -2 10 -1 1 0.2 0.1 0.05 0.02 duty cycle = 0.5 single pulse normalized ef fective transient thermal impedance
package information www.vishay.com vishay siliconix revison: 30-sep-13 1 document number: 71198 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 to-263 (d 2 pak): 3-lead notes 1. plane b includes maximum featur es of heat sink tab and plastic. 2. no more than 25 % of l1 ca n fall above seating plane by max. 8 mils. 3. pin-to-pin coplanarity max. 4 mils. 4. *: thin lead is for sub, syb. thick lead is for sum, sym, sqm. 5. use inches as the primary measurement. 6. this feature is for thick lead. -a- -b- d1 d4 a a e b2 b e a c2 c l2 d l3 l detail ?a? e1 e2 k e3 d2 d3 6 0.010 m a m 2 pl detail a (rotated 90) s ection a-a 0 - 5 l1 l4 m c1 c b1 b inches millimeters dim. min. max. min. max. a 0.160 0.190 4.064 4.826 b 0.020 0.039 0.508 0.990 b1 0.020 0.035 0.508 0.889 b2 0.045 0.055 1.143 1.397 c* thin lead 0.013 0.018 0.330 0.457 thick lead 0.023 0.028 0.584 0.711 c1 thin lead 0.013 0.017 0.330 0.431 thick lead 0.023 0.027 0.584 0.685 c2 0.045 0.055 1.143 1.397 d 0.340 0.380 8.636 9.652 d1 0.220 0.240 5.588 6.096 d2 0.038 0.042 0.965 1.067 d3 0.045 0.055 1.143 1.397 d4 0.044 0.052 1.118 1.321 e 0.380 0.410 9.652 10.414 e1 0.245 - 6.223 - e2 0.355 0.375 9.017 9.525 e3 0.072 0.078 1.829 1.981 e 0.100 bsc 2.54 bsc k 0.045 0.055 1.143 1.397 l 0.575 0.625 14.605 15.875 l1 0.090 0.110 2.286 2.794 l2 0.040 0.055 1.016 1.397 l3 0.050 0.070 1.270 1.778 l4 0.010 bsc 0.254 bsc m - 0.002 - 0.050 ecn: t13-0707-rev. k, 30-sep-13 dwg: 5843
an826 vishay siliconix document number: 73397 11-apr-05 www.vishay.com 1 recommended minimum pads for d 2 pak: 3-lead 0.635 (16.129) recommended minimum pads dimensions in inches/(mm) 0.420 (10.668) 0.355 (9.017) 0.145 (3.683) 0.135 (3.429) 0.200 (5.080) 0.050 (1.257) return to index
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